Device for probe card power bus noise reduction
US7005879B1 · kind B1 · utility
96Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 1, 2005 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Mar 1, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Noise reduction for application of structural test patterns to a Device Under Test (DUT) is accomplished with a capacitor “booster” bypass network on the probe card in which the capacitors are charged to a much higher voltage Vboost than the DUT power supply voltage VDD. Charging the capacitors to a voltage N×VDD allows the buster network to store N times the charge of a conventionally configured capacitance network, and effectively provides N times the capacitance of the original network in the same physical space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.