Feed-forward circuit for reducing delay through an input buffer
US7005910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2004 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jan 16, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01707
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An invention is provided for a feed forward circuit that reduces delay through an inverting circuit. The feed forward circuit includes an inverter having an input and an output, and an inverting circuit having an input and an output. The input of the inverting circuit is coupled to the output of the inverter. A feed forward transistor having a gate coupled to the input of the inverter and a terminal coupled to the output of the inverting circuit also is included. In operation the feed forward transistor decreases the amount of time required for the output of the inverting circuit to change state. In sum, the invention reduces the delay when the inverting circuit transitions to a high state, without affecting the timing of the transition to a low state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.