Brian Reed
8Patents
4h-index
13Co-inventors
50Inventor score
Filing activity: Jul 29, 2003 → Oct 25, 2013
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8225239B2 | Methods for defining and utilizing sub-resolution features in linear topology | Emerging Cross-Sectional Technologies | 114 | Active |
| US8448102B2 | Optimizing layout of irregular structures in regular layout context | Emerging Cross-Sectional Technologies | 103 | Active |
| US9122832B2 | Methods for controlling microloading variation in semiconductor wafer layout and fabrication | Emerging Cross-Sectional Technologies | 9 | Active |
| US9754878B2 | Semiconductor chip including a chip level based on a layout that includes both regular and irregular wires | Emerging Cross-Sectional Technologies | 5 | Active |
| US7005910B2 | Feed-forward circuit for reducing delay through an input buffer | Electricity | 3 | Expired |
| US6924687B2 | Voltage tolerant circuit for protecting an input buffer | Electricity | 1 | Expired |
| US8680912B2 | Level shifting circuitry | Electricity | 1 | Active |
| US9070431B2 | Memory circuitry with write assist | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.