Method and apparatus for interfacing a processor to a coprocessor
US7007154B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2001 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jan 14, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor (12) to coprocessor (14) interface supporting multiple coprocessors (14, 16) utilizes compiler generatable software type function call and return, instruction execute, and variable load and store interface instructions. Data is moved between the processor (12) and coprocessor (14) on a bi-directional shared bus (28) either implicitly through register snooping and broadcast, or explicitly through function call and return and variable load and store interface instructions. The load and store interface instructions allow selective memory address preincrementation. The bi-directional bus (28) is potentially driven both ways on each clock cycle. The interface separates interface instruction decode and execution. Pipelined operation is provided by indicating decoded instruction discard by negating a decode signal before an execute signal is asserted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.