Multiple coprocessor architecture to process a plurality of subtasks in parallel
US7007156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2000 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Oct 11, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/5017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmed state processing machine architecture and method that provides improved efficiency for processing data manipulation tasks. In one embodiment, the processing machine comprises a control engine and a plurality coprocessors, a data memory, and an instruction memory. A sequence of instructions having a plurality of portions are issued by the instruction memory, wherein the control engine and each of the processors is caused to perform a specific task based on the portion of the instructions designated for that component. Accordingly, a data manipulation task can be divided into a plurality of subtasks that are processed in parallel by respective processing components in the architecture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.