Method and apparatus for power consumption analysis in global nets
US7007256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Jul 13, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention describes a method and an apparatus for determining switching power consumption of global devices (e.g., repeaters, flops or the like) in an integrated circuit design during high-level design phase after the global routing for the integrated circuit is available. The clock cycle is divided into various timing intervals and the timing reports are generated for each cycle to determine a time-domain staggered distribution of each device's switching activity within a given timing interval. Each device's switching activity is analyzed within the given timing interval (or segment thereof). The power consumption is determined for each device that switches in the given timing interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.