Peter Lai
13Patents
4h-index
35Co-inventors
52Inventor score
Filing activity: Jun 13, 2000 → Jan 2, 2008
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7109757B2 | Leakage-tolerant dynamic wide-NOR circuit structure | Electricity | 23 | Expired |
| US7036096B1 | Estimating capacitances using information including feature sizes extracted from a netlist | Physics | 17 | Expired |
| US7890909B2 | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow | Physics | 12 | Active |
| US7007256B2 | Method and apparatus for power consumption analysis in global nets | Physics | 9 | Expired |
| US6954914B2 | Method and apparatus for signal electromigration analysis | Physics | 4 | Expired |
| US7284215B1 | Method to solve similar timing paths | Physics | 4 | Expired |
| US6775813B2 | Aggregation of storage elements into stations and placement of same into an integrated circuit or design | Physics | 4 | Expired |
| US6654942B2 | Method and system for providing a netlist driven integrated router in a non-netlist driven environment | Physics | 3 | Expired |
| US7484193B2 | Method and software for predicting the timing delay of a circuit path using two different timing models | Physics | 1 | Expired |
| US7032200B1 | Low threshold voltage transistor displacement in a semiconductor device | Physics | 1 | Expired |
| US6596563B2 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Electricity | 1 | Expired |
| US6779131B2 | Reconfigurable multi-chip modules | Physics | 1 | Expired |
| US6396149B1 | Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.