Design flow method for integrated circuits
US7007263B2 · kind B2 · utility
4Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2003 |
| Grant date | Feb 28, 2006 |
| Priority date | — |
| Expiry date | Feb 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318594
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The design flow method of the present invention accurately performs timing analysis during the circuit design stage, so that the DFT synthesis procedure can effectively control the timing information, preventing timing violation from happening during the IC design flow process. Furthermore, the information of the CTS procedure and the static-timing analysis procedure is combined to perform accurate timing estimation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.