Chun-Chih Yang
10Patents
3h-index
10Co-inventors
57Inventor score
Filing activity: May 6, 1999 → Dec 29, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6467072B1 | Method of placement and routing for an array device | Physics | 112 | Expired |
| US6405356B1 | Method of automatic placement for an arrayed-element device | Physics | 9 | Expired |
| US7007263B2 | Design flow method for integrated circuits | Physics | 4 | Expired |
| US9892226B2 | Methods for providing macro placement of IC | Emerging Cross-Sectional Technologies | 1 | Active |
| US9940422B2 | Methods for reducing congestion region in layout area of IC | Electricity | 1 | Active |
| US9946829B2 | Methods for redistributing cell densities in layout area of IC | Physics | 0 | Active |
| US9817936B2 | Methods for minimizing layout area of IC | Physics | 0 | Active |
| US11803539B2 | Method of improving efficiency of updating data as to rules stored in block chain, electronic device, and computer readable storage medium applying the method | Electricity | 0 | Active |
| US10162927B2 | Methods for redistributing cell densities in layout area of IC | Physics | 0 | Active |
| US7526703B2 | Method of test pattern generation in IC design simulation system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.