Electrostatic discharge protection device for integrated circuits
US7009229B1 · kind B1 · utility
10Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Mar 3, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
Abstract
A protection device for integrated circuits. A complementary well is fabricated in a semiconductor substrate. An enhancement mode junction field effect transistor (JFET) is fabricated in the complementary well. An interface bonding pad is fabricated above the JFET. A source contact is also fabricated in the well. The gate and drain of the JFET are coupled to the interface bonding pad and the source of the JFET is coupled to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.