Substrate for stressed systems and method of making same
US7009270B2 · kind B2 · utility
4Cited by
4References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Apr 4, 2024 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB81C2201/0191
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stress absorbing microstructure assembly including a support substrate having an accommodation layer that has plurality of motifs engraved or etched in a surface, a buffer layer and a nucleation layer. The stress absorbing microstructure assembly may also include an insulating layer between the buffer layer and the nucleation layer. This assembly can receive thick epitaxial layers thereon with concern of causing cracking of such layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.