Multi-chip module
US7009303B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Oct 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed here is a multi-chip module enhanced in performance and reduced in size. A second semiconductor chip having bonding pads at the periphery of its surface is mounted over a first semiconductor chip laid out over a surface of a substrate back to back and a spacer is provided at a portion of the second semiconductor chip surface except for a predetermined area that includes the portion where the bonding pads are formed while a third semiconductor chip is mounted over the spacer, the third semiconductor having the same circuit function as the second semiconductor chip and oriented similarly to the second semiconductor chip. The bonding pads of the second and third semiconductor chips are connected to their corresponding electrodes formed over the substrate through bonding wires respectively, then the first to third semiconductor chips and the bonding wires provided over the substrate are all sealed by a sealing agent.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.