Field programmable gate array core cell with efficient logic packing
US7009421B2 · kind B2 · utility
3Cited by
1References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2004 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Sep 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.