Event pipeline and summing method and apparatus for event based test system
US7010452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Oct 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31932
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An event pipeline and vernier summing apparatus for high speed event based test system processes the event data to generate drive events and strobe events with various timings at high speed to evaluate a semiconductor device under test. The event pipeline and vernier summing apparatus is configured by an event count delay logic, a vernier data decompression logic, an event vernier summation logic, an event scaling logic, and a window strobe logic. The event pipeline and summing method and apparatus of the present invention is designed to perform high speed event timing processing with use of a pipeline structure. The window strobe logic provides a function for detecting a window strobe request and generating a window strobe enable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.