Built-in test support for an integrated circuit
US7010732B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2002 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Jun 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Test circuitry for testing an integrated circuit, the integrated circuit being configurable to accept input data from stimulus scan cells and to provide output data to response scan cells, the test circuitry including stimulus circuitry for providing test data to the integrated circuit; input selection means operable to control which of the test data and the input data are received at the integrated circuit; capture circuitry for capturing output data from the integrated circuit and generating response data; output selection means operable to select which of the output data and the response data are received by the response scan cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.