Parametric testing for high pin count ASIC

US7010733B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert W. Bassett · South Burlington, US
• Garrett S Christensen · Endicott, US
• Michael Combs · South Burlington, US
• L. Farnsworth · Middlebury, US
• Pamela S. Gillis · Jericho, US

Key dates

• Filing date: Oct 9, 2002
• Grant date: Mar 7, 2006
• Expiry date: May 19, 2023

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/3004
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method for reducing Pin Count Test design and test that allows parametric test patterns for high pin count ASICs to be applied using low pin count testers. The same boundary scan structure used to isolate the test of internal logic to a small number of test I/O is also used to apply parametric external I/O tests to the ASIC's functional I/O. The parametric tests are banked into pin groups and applied on the same low pin count tester used for the internal logic tests.