Method of optimizing and analyzing selected portions of a digital integrated circuit
US7010763B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2003 |
| Grant date | Mar 7, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for achieving timing closure in the design of a digital integrated circuit or system by selecting portions of the circuit or system to be optimized and portions of the circuit or system in which the effects of such optimization are to be analyzed during the optimization process. Optimized portions will include gates whose design parameters are to be changed, a first analyzed portion includes gates whose delays and edge slews are to be recomputed, and a second analyzed portion includes gates whose ATs and RATs are to be recomputed during optimization. Constraints are imposed at selected boundaries between these portions to prevent unwanted propagation of timing information and to ensure the validity of timing values used during optimization. Through this selection, the size of the problem posed to the underlying optimization method will be reduced, allowing larger circuits or systems to be optimized and allowing optimization to be performed more quickly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.