Circuit configuration and method for reducing the 1/f noise of MOSFETs

US7012468B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Ralf Brederlow · Poing, DE
• Roland Thewes · Puchheim, DE

Key dates

• Filing date: Jul 15, 2002
• Grant date: Mar 14, 2006
• Expiry date: Nov 13, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

The circuit configuration and the associated method allow reducing the 1/f noise of MOSFETs in an electronic circuit, especially in an integrated circuit with one or more MOSFETs. At least one direct current and/or at least one direct voltage source for adjusting constant working point(s) of the MOSFET(s) is/are assigned to one or more or all MOSFETs. At least one periodically oscillating current and/or voltage source is assigned to one or more or all MOSFETs so that the respective working points periodically oscillate about the constant working point(s) in such a manner that impurity states in the oxide of the MOSFET, which are recharged under the condition of a constant working point according to the principles of statistics such that they determine the 1/f noise signal, are no longer recharged statistically but at a lower probability due to the modulatory frequency of the periodically oscillating sources.