Method for stress reduction in flip chip bump during flip chip mounting and underfill process steps of making a microelectronic assembly
US7015066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2001 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jul 31, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53265
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a microelectronic assembly buying restraining a substrate in a fixture at room temperature, placing a flip chip on the substrate so that conductive bumps on the flip chip are aligned with contact pads on the substrate, heating the flip chip, the substrate and the fixture to reflow the conductive bumps on the flip chip, cooling the flip chip, substrate and fixture to solidify the conductive bumps and to mount the flip chip to the substrate, depositing an underfill between the flip chip and the substrate, curing the underfill by heating the flip chip, substrate, underfill and fixture to an elevated temperature, and removing the flip chip mounted substrate from the fixture.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.