Double gate field effect transistor and method of manufacturing the same
US7015106B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 11, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.