Method and structure of manufacturing high capacitance metal on insulator capacitors in copper
US7015110B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 6, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Feb 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved semiconductor integrated circuit device structure. The device structure includes a substrate. A thickness of first insulating material is overlying the substrate. A capacitor region within the thickness of the first insulating material and extends from a lower surface of the first insulating material to an upper surface of the first insulating material. The capacitor region includes a width, which extends from the lower surface to the upper surface. The width may vary slightly in some embodiments. The structure includes a contact region overlying the substrate within at least the capacitor region. A lower capacitor plate formed from a plurality of vertical metal structures defined within the capacitor region and connected to the contact region. Each of the plurality of vertical metal structures includes a width and a height. Each of the plurality of vertical metal structures is substantially parallel to each other along a length of the height of each of the vertical metal structures. A barrier metal layer is formed overlying exposed surfaces of each of the plurality of vertical metal structures. A capacitor dielectric layer is overlying each of the exposed surfaces of t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.