Method of forming silicided gate structure
US7015126B2 · kind B2 · utility
12Cited by
44References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jun 3, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.