Simplified dual damascene process
US7015149B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Oct 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76808
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.