Semiconductor memory device
US7015540B2 · kind B2 · utility
15Cited by
1References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 15, 2003 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Oct 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To realize a semiconductor memory device with reduced cell-to-cell variation in writing characteristics a semiconductor memory has a source region and a drain region, which are formed parallel to each other, and an assist electrode which is between and parallel to the source and drain regions without overlapping, so that at the time of writing, the assist electrode is used as an assist electrode for hot electrons to be injected at the source side and at the time of reading, an inversion layer formed under the assist electrode is used as the source region or the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.