CMOS output buffer circuit
US7015731B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0036
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS output buffer circuit comprises an input unit, a compensation control unit, a first switching unit and a second switching unit. The input unit outputs a data signal in response to a stop signal for determining transmission of the data signal. The compensation control unit determines a power voltage level with reference to the stop signal and the data signal when the data signal is transmitted, and outputs a plurality of compensating signals depending on the power voltage level. The first switching unit including a driving unit driven by the data signal outputted from the input unit and a compensation driving unit driven by combination of the data signal and the plurality of compensating signals compensates change of the power voltage level to output current. The second switching unit operated complementarily with the first switching unit outputs current. Accordingly, the CMOS output buffer circuit supplies a predetermined output current regardless change of a power voltage, thereby reducing power consumption and minimizing overshoot/undershoot noise to stabilize a power supplied to a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.