EEPROM memory matrix and method for safeguarding an EEPROM memory matrix
US7015821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 12, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
EEPROM memory matrix in which column lines are alternatively used as detector lines. A precharge voltage is applied to selected detector lines together with the relevant column line in each case before read-out of the memory columns. If a detector line loses its precharge level during the read-out of the memory cells, light incidence is assumed and a corresponding alarm function is triggered. Preferably column lines adjacent to the column lines that are respectively selected for the data transmission are connected as detector lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.