Multi-port memory device
US7016255B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jul 31, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-port memory device can avoid failure of the first high data during initial operation so that reliability and operation characteristic of the memory device can be improved. The multi-port memory device comprises a global data bus having a multiplicity of bus lines, a plurality of banks having a current sensing type transceiving structure for exchanging data with the global data bus, one or more ports having a current sensing type transceiving structure for exchanging data with the global data bus, a plurality of switches, each arranged between the corresponding bank and the bus lines of the global data bus for selectively connecting one of a redundant column and normal columns of the corresponding bank to the global data bus, and a controlling unit for restricting the turn-on period of the switches to the substantial operation period of the corresponding bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.