Method for error control in multilevel cells with configurable number of stored bits
US7017099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2002 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Nov 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.