Roberto Ravasio
26Patents
9h-index
25Co-inventors
75Inventor score
Filing activity: Apr 16, 1992 → Jan 29, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7366014B2 | Double page programming system and method | Physics | 26 | Active |
| US7800943B2 | Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings | Physics | 20 | Active |
| US7362616B2 | NAND flash memory with erase verify based on shorter evaluation time | Physics | 18 | Active |
| US5418849A | Procedure and device for adaptive digital cancellation of the echo generated in telephone connections with time-variant characteristics | Electricity | 17 | Expired |
| US7336538B2 | Page buffer circuit and method for multi-level NAND programmable memories | Physics | 15 | Active |
| US7382660B2 | Method for accessing a multilevel nonvolatile memory device of the flash NAND type | Physics | 12 | Active |
| US7017099B2 | Method for error control in multilevel cells with configurable number of stored bits | Physics | 11 | Expired |
| US7394694B2 | Flash memory device with NAND architecture with reduced capacitive coupling effect | Physics | 10 | Active |
| US7730357B2 | Integrated memory system | Physics | 9 | Expired |
| US8966335B2 | Method for performing error corrections of digital information codified as a symbol sequence | Electricity | 9 | Active |
| US7031193B2 | Method and device for programming an electrically programmable non-volatile semiconductor memory | Physics | 8 | Expired |
| US7940575B2 | Memory device and method providing logic connections for data transfer | Emerging Cross-Sectional Technologies | 6 | Active |
| US7581153B2 | Memory with embedded error correction codes | Physics | 5 | Active |
| US8065467B2 | Non-volatile, electrically-programmable memory | Physics | 5 | Active |
| US7328397B2 | Method for performing error corrections of digital information codified as a symbol sequence | Electricity | 4 | Expired |
| US7529136B2 | Method for compacting the erased threshold voltage distribution of flash memory devices during writing operations | Physics | 4 | Active |
| US7068540B2 | Method and device for programming an electrically programmable non-volatile semiconductor memory | Physics | 3 | Expired |
| US7221602B2 | Memory system comprising a semiconductor memory | Physics | 3 | Expired |
| US7035142B2 | Non volatile memory device including a predetermined number of sectors | Physics | 2 | Expired |
| US7908543B2 | Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code | Physics | 2 | Active |
| US7937576B2 | Configuration of a multi-level flash memory device | Physics | 1 | Active |
| US10630317B2 | Method for performing error corrections of digital information codified as a symbol sequence | Electricity | 0 | Active |
| US6956773B2 | Circuit for programming a non-volatile memory device with adaptive program load control | Physics | 0 | Expired |
| US7719894B2 | Method of programming cells of a NAND memory device | Physics | 0 | Active |
| US8347201B2 | Reading method of a memory device with embedded error-correcting code and memory device with embedded error-correcting code | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.