Device and method for Viterbi equalization with metric increments calculated in advance
US7017103B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2003 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Sep 11, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A Viterbi equalizer for equalization of a data signal transmitted via a channel that is subject to interference has at least one add-compare-select unit (ACS), which carries out an ACS operation for each channel state in a time step k. Furthermore, the equalizer has a unit for calculating metric increments in advance and for storing the metric increments. The calculation unit calculates in advance the metric increments relating to all the transitions from a state which can be predetermined in the time step k to the states which can be reached by the transitions in the time step k+1. The metric increments are retained in an output memory such that they can be called up for utilization in the ACS unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.