Method of making a device threshold control of front-gate silicon-on-insulator MOSFET using a self-aligned back-gate
US7018873B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Dec 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6744
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.