Method for a parallel production of an MOS transistor and a bipolar transistor

US7018884B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Adrian Berthold · Birkenfeld, DE
• Josef Bock · Birkenfeld, DE
• Jürgen Holz · Birkenfeld, DE
• Wolfgang Klein · Zorneding, DE

Key dates

• Filing date: Feb 6, 2004
• Grant date: Mar 28, 2006
• Expiry date: Feb 14, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

The present invention provides a method for parallel production of an MOS transistor in an MOS area of a substrate and a bipolar transistor in a bipolar area of the substrate. The method comprises generating an MOS preparation structure in the MOS area, wherein the MOS preparation structure comprises an area provided for a channel, a gate dielectric, a gate electrode layer and a mask layer on the gate electrode layer. Further, a bipolar preparation structure is generated in the bipolar area, which comprises a conductive layer and a mask layer on the conductive layer. The mask layer is thinned in the area of the gate electrode. For determining a gate electrode and a base terminal area, common structuring of the gate electrode layer and the conductive layer is performed.