Transistor with strain-inducing structure in channel

US7019326B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Stephen M. Cea · Hillsboro, US
• Ravindra Soman · Portland, US
• Ramune Nagisetty · Portland, US
• Sunit Tyagi · Portland, US
• Sanjay Natarajan · Portland, US

Key dates

• Filing date: Nov 14, 2003
• Grant date: Mar 28, 2006
• Expiry date: Nov 14, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/791

Abstract

Various methods for forming a layer of strained silicon in a channel region of a device and devices constructed according to the disclosed methods. In one embodiment, a strain-inducing layer is formed, a relaxed layer is formed on the strain-inducing layer, a portion of the strain-inducing layer is removed, which allows the strain-inducing layer to relax and strain the relaxed layer.