Stephen M. Cea
126Patents
15h-index
97Co-inventors
89Inventor score
Filing activity: Mar 31, 2003 → Jan 10, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7154118B2 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication | Electricity | 208 | Expired |
| US8753942B2 | Silicon and silicon germanium nanowire structures | Electricity | 131 | Active |
| US7326634B2 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication | Electricity | 68 | Expired |
| US8211772B2 | Two-dimensional condensation for uniaxially strained semiconductor fins | Electricity | 60 | Active |
| US9129829B2 | Silicon and silicon germanium nanowire structures | Electricity | 58 | Active |
| US6982433B2 | Gate-induced strain for MOS performance improvement | Electricity | 43 | Expired |
| US8847281B2 | High mobility strained channels for fin-based transistors | Electricity | 39 | Active |
| US9224810B2 | CMOS nanowire structure | Electricity | 32 | Active |
| US8120073B2 | Trigate transistor having extended metal gate electrode | Electricity | 27 | Active |
| US7019326B2 | Transistor with strain-inducing structure in channel | Electricity | 24 | Expired |
| US9583491B2 | CMOS nanowire structure | Electricity | 24 | Active |
| US7781771B2 | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication | Electricity | 24 | Active |
| US6936505B2 | Method of forming a shallow junction | Electricity | 22 | Expired |
| US7973389B2 | Isolated tri-gate transistor fabricated on bulk substrate | Electricity | 22 | Active |
| US9608059B2 | Semiconductor device with isolated body portion | Electricity | 16 | Active |
| US8269283B2 | Methods and apparatus to reduce layout based strain variations in non-planar transistor structures | Electricity | 15 | Active |
| US7045408B2 | Integrated circuit with improved channel stress properties and a method for making it | Electricity | 14 | Expired |
| US9224808B2 | Uniaxially strained nanowire structure | Electricity | 13 | Active |
| US8957476B2 | Conversion of thin transistor elements from silicon to silicon germanium | Electricity | 12 | Active |
| US8558279B2 | Non-planar device having uniaxially strained semiconductor body and method of making same | Electricity | 11 | Active |
| US9570614B2 | Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation | Electricity | 11 | Active |
| US9472613B2 | Conversion of strain-inducing buffer to electrical insulator | Electricity | 11 | Active |
| US7102141B2 | Flash lamp annealing apparatus to generate electromagnetic radiation having selective wavelengths | Electricity | 11 | Expired |
| US9129827B2 | Conversion of strain-inducing buffer to electrical insulator | Electricity | 9 | Active |
| US10304946B2 | Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.