Circuit package and method of plating the same
US7019394B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09354
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A circuit package includes a base portion and a first metal pattern disposed on a substrate surface. Second and third metal patterns are disposed on another substrate surface, and electrically coupled to first and second vias. The third metal pattern forms a gap to electrically isolate it from the second metal pattern. A circuit package includes a substrate having an opening and a single heat sink positioned in the opening to expose top and bottom surfaces through top and bottom surfaces of the substrate. Selective plating includes applying first and second metal patterns to a substrate surface, creating a potential voltage difference between the first metal pattern and a metal source, and plating the first metal pattern by attracting a first metal type to the voltage potential of the first metal pattern. The voltage potential of the first metal pattern is less than the voltage potential of the metal source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.