Method and circuit for off chip driver control, and memory device using same
US7019553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Apr 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.