Circuit for performing on-die termination operation in semiconductor memory device and its method
US7019555B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0278
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for performing an on-die termination operation includes a clock buffer for outputting first and second buffered clocks using an external clock and an external inverting clock applied thereto externally; an on-die termination buffer for comparing each other an ODT signal and a reference voltage, which are applied thereto from an external chip set, to generate an on-die termination comparison signal; a first flip-flop member for transferring the on-die termination comparison signal as a plurality of parallel output signals based on the first and second buffered clocks outputted from the clock buffer; and a plurality of second flip-flop members, which corresponds to each of the parallel output signals outputted from the first flip-flop member, for transferring the parallel output signals outputted from the first flip-flop member based on delayed lock loop clocks outputted from a delayed lock loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.