Delay circuit that scales with clock cycle time
US7019576B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2004 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Mar 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/265
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit having a process, voltage, and temperature (PVT) invariant delay element is disclosed. In one embodiment, the present invention includes a first and second operational transconductance amplifier (OTA), a first and second switched capacitor driven by a clock, and a first and second clock-controlled switch. In addition, the present invention includes a trip inverter, a delay inverter, and a plurality of transistors. In so coupling the first and second OTA, the first and second switched capacitor, the first and second clock-controlled switch, the trip inverter, the delay inverter, and the plurality of transistors, a circuit having a PVT invariant delay element is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.