Inventor · Starkville, MS, US

Suwei Chen

5Patents
4h-index
5Co-inventors
39Inventor score

Filing activity: Mar 18, 2004 → Jun 30, 2006

Most-cited inventions

PatentTitleAreaCited byStatus
US7135899B1 System and method for reducing skew in complementary signals that can be used to synchronously clock a double data rate output Electricity 16 Expired
US7019576B1 Delay circuit that scales with clock cycle time Electricity 10 Expired
US7545194B2 Programmable delay for clock phase error correction Electricity 9 Active
US7132854B1 Data path configurable for multiple clocking arrangements Electricity 9 Expired
US7339403B2 Clock error detection circuits, methods, and systems Electricity 4 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.