Non-switching pre- and post- disturb compensational pulses
US7020005B2 · kind B2 · utility
2Cited by
4References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 10, 2005 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Feb 10, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a passive matrix addressable ferroelectric device having a voltage pulse protocol with a pre-disturb and post-disturb cycle before and after a disturb generating operation cycle respectively in order to minimize the effect of disturb voltage on non-addressed memory cells, when such voltages are generated thereto in the operation cycle when It is applied for either a write or read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.