Semiconductor memory device
US7020043B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2005 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jul 12, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor memory device that is capable of preventing unnecessary power consumption and providing high data reliability. The semiconductor memory device includes: a core voltage supplying part for supplying a core voltage; a memory cell array block; a bit line sense amplifier block for sensing and amplifying a voltage difference of bit line pairs of the memory cell array block; an overdriving signal generator for receiving an initial driving signal to generate an overdriving signal, while expanding an activation pulse width of the overdriving signal in an activation of a refresh signal; an overdriver for driving a connection node, which is coupled with the core voltage supplying part, to an external voltage higher than the core voltage in response to an inverted overdriving signal; a first power driver for driving a first power line of the bit line sense amplifier block to a voltage of the connection node in response to a first driving control signal; and a second power driver for driving a second power line of the bit line sense amplifier to a first power voltage in response to a second driving control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.