Reduced power option
US7020788B2 · kind B2 · utility
3Cited by
209References
33Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 1, 2001 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jun 14, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a clock source change or inhibit. This instruction may be executed in one processor cycle and with one power mode instruction employing clock transition logic within the processor to initiate a switch to the clock source configuration specified by a literal, such as a 3-bit literal. Operand may be written the register of clock transition logic to define an exit state for a sleep mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.