Processor core and methods to reduce power by not using components dedicated to wide operands when a micro-instruction has narrow operands
US7020789B2 · kind B2 · utility
5Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Apr 2, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In some embodiments of the present invention, one or more elements of a processor core may receive a signal indicating that operands of a micro-instruction are narrow, for example less than or equal to 32 bits. In response to this signal, one or more components of a processor core element that are able to handle more than 32 bits of data (e.g. operands or results) may function as though they handle only 32 bits of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.