Latch placement technique for reduced clock signal skew
US7020861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing an integrated circuit including executing a placement algorithm to place a set of objects within the integrated circuit. The set of objects includes latched objects and non-latched objects. The algorithm places objects to minimize clock signal delay subject to a constraint on the placement distribution of the latched objects relative to the placement distribution of the non-latched objects. The latched object and non-latched object placement constraints may limit the difference between the latched object center of mass and a non-latched object center of mass. The latched object center of mass equals a sum of size-location products for each latched object divided by the sum of sizes for each latched object. The constraints may require that the latched object center of mass and the non-latched center of mass both equal the center of mass for all objects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.