Hybrid magnetoresistive random access memory (MRAM) architecture
US7023726B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2005 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a hybrid MRAM architecture, and more particularly to a hybrid MRAM architecture capable of being used with an MCU and an MPU. This hybrid MRAM architecture is adapted to a controlling device for accessing a bit of information, comprising a plurality of first MRAM arrays (1T1MTJ architecture), a plurality of second MRAM arrays (XPC architecture), an address line, an access decoder, a sensing and writing circuit, and at least one I/O bus. The access decoder accesses to the bit of information from either the first or the second MRAM arrays selected in accordance with an address signal from the controlling device. The sensing and writing circuit amplifies the bit of information and transmits it to the controlling device via the at least one I/O bus. Accordingly, the access of the bit of information is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.