Memory arrangement for processing data, and method
US7023760B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Aug 22, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.