Techniques for automatically generating tests for programmable circuits

US7024327B1 · kind B1 · utility

Assignee

• Altera Corporation · US

Inventors

• Jayabrata Ghosh Dastidar · Santa Clara, US
• Adam Wright · Santa Clara, US
• Hung Hing Anthony Pang · San Jose, US
• Binh Vo · Los Gatos, US
• Ajay Nagarandal · Sunnyvale, US
• Paul Tracy · Sunnyvale, US
• Michael Harms · Frankfurt am Main, DE

Key dates

• Filing date: Dec 18, 2002
• Grant date: Apr 4, 2006
• Expiry date: Dec 27, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318307
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Programmable circuits have a programmable interconnect structure that connects programmable circuit elements. Tests patterns can be automatically generated for the programmable circuit elements and interconnections on a programmable circuit. A connectivity graph represents programmable interconnections and functions as nodes. Tests routes are generated that connect the nodes in the connectivity graph between control points and observation points on the programmable circuit. The routes are grouped into configuration patterns that can be tested in one test cycle. Test vectors are then applied to the routes to determine if the interconnects and circuit functions are operable. Systems and methods of the present invention automatically create test patterns for a programmable circuit to reduce engineer time. The present invention also reduces test time and resources by increasing the number of interconnections and circuit elements tested in each configuration pattern.