IC signal path resistance estimation method
US7024644B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2003 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Aug 21, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99943
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Diffusion effects during an IC fabrication process cause actual dimensions of adjacent conductors in an IC to vary from nominal dimensions specified by data defining the IC layout. A computer-aided design tool processes the layout data to generate a separate database for each layer of the IC, including a separate table corresponding to each grid line of that layer. Each table includes a separate table entry corresponding to each conductor to reside along the table's corresponding grid line, each table entry indicating nominal dimensions and position of its corresponding conductor. The tool sorts grid line tables within each layer's database in an order in which their corresponding grid lines are arranged on that layer, and sorts entries in each table in an order in which their corresponding conductors are to appear along the table's corresponding grid line. The tool then reads each entry in each table of each database only once, in the orders in which the entries and tables are sorted, to obtain information it needs to estimate actual dimensions of each conductor, and estimates the resistance of each conductor as a function of its estimated actual dimensions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.