Low profile chip scale stacking system and method
US7026708B2 · kind B2 · utility
69Cited by
241References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2003 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Aug 3, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention stacks chip scale-packaged integrated circuits (CSPs) into low profile modules that conserve PWB or other board surface area. Low profile contacts are created by any of a variety of methods and materials. A consolidated low profile contact structure and technique is provided for use in alternative embodiments of the present invention. Multiple numbers of CSPs may be stacked in accordance with the present invention. The CSPs employed in stacked modules devised in accordance with the present invention are connected with flex circuitry that exhibit one or two or more conductive layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.