High-speed semiconductor memory having internal refresh control
US7027344B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Jul 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores the refresh count address, and the addresses stored in the counter and the shift registers prior to the increment operation is shifted out and stored in a pipelined fashion. If the array address stored in the last stage of the register pipeline is equal to the address of the array read out during the cycle immediately preceding the refresh cycle or is equal to the address of the neighboring array of the read out array, the comparator causes multiplexer to select the address stored in the counter as the refresh address. This address differs from the address of the array read out during the immediately preceding cycle by at least two counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.